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december 2007 rev 9 1/47 1 m45pe80 8 mbit, low voltage, page-erasable serial flash memory with byte alterability and a 50 mhz spi bus interface features spi bus compatible serial interface 50 mhz clock rate (maximum) 2.7 v to 3.6 v single supply voltage 8 mbit of page-erasable flash memory page size: 256 bytes: ? page write in 11 ms (typical) ? page program in 0.8 ms (typical) ? page erase in 10 ms (typical) sector erase (64 kbytes) hardware write protection of the bottom sector (64 kbytes) electronic signature ? jedec standard two-byte signature (4014h) deep power-down mode 1 a (typical) more than 100 000 write cycles more than 20 years? data retention packages ? ecopack? (rohs compliant) vfqfpn8 (mp) 6 5 mm (mlp8) so8w (mw) 208 mils width so8n (mn) 150 mils width www.numonyx.com
contents m45pe80 2/47 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 reset (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 an easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 a fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 active power, stand-by power and deep power-down modes . . . . . . . . 13 4.7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m45pe80 contents 3/47 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . 22 6.7 page write (pw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.8 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.9 page erase (pe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12 release from deep power-down (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables m45pe80 4/47 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. power-up timing and vwi threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. ac characteristics (25 mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. ac characteristics (33 mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. ac characteristics (50 mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 15. reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16. timings after a reset low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. vfqfpn8 (mlp8)8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. so8 wide ? 8 lead plastic small outline, 20 8 mils body width, mechanical data. . . . . . . . 42 table 19. so8n - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
m45pe80 list of figures 5/47 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. vfqfpn and so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . . . . 19 figure 9. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . 20 figure 10. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 21 figure 11. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. page write (pw) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 13. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. page erase (pe) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 15. sector erase (se) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 16. deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. release from deep power-down (rdp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. write protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23. reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline . . . . . . . . 42 figure 26. so8n - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 43
summary description m45pe80 6/47 1 summary description the m45pe80 is a 8 mbit (1 mbit 8 bit) serial paged flash memory accessed by a high speed spi-compatible bus. the memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. the page write instruction consists of an integrated page erase cycle followed by a page program cycle. the memory is organized as 16 sectors, each containing 256 pages. each page is 256 bytes wide. thus, the whole memory can be view ed as consisting of 4096 pages, or 1 048 576 bytes. the memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction. in order to meet environmental requirements, numonyx offers the m45pe80 in ecopack? packages. ecopack? packages are lead-free and rohs compliant. figure 1. logic diagram table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input reset reset input v cc supply voltage v ss ground reset ai06810b s v cc m45pe80 v ss w q c d
m45pe80 summary description 7/47 figure 2. vfqfpn and so connections 1. there is an exposed central pad on the underside of the vfqfpn package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see section 11: package mechanical for package dimensions, and how to identify pin-1. 1 ai06811b 2 3 4 8 7 6 5 w s v cc v ss c dq reset m45pe80
signal description m45pe80 8/47 2 signal description 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal read, progra m, erase or write cycle is in progress, the device will be in the standby mode (this is not the deep po wer-down mode). driving chip select (s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 reset (reset ) the reset (reset ) input provides a hardware reset for the memory. when reset (reset ) is driven high, the memory is in the normal operating mode. when reset (reset ) is driven low, the device enters the reset mode. in this mode, the output q is high impedance: if an internal operation (write, erase or program cycle) is in progress when reset (reset ) is driven low, the device enters the reset mode and any on-going write, program or erase cycle is aborted. the addressed data may be lost. 2.6 write protect (w ) this input signal puts the device in the hardware protected mode, when write protect (w ) is connected to v ss , causing the first 256 pages of memory to become read-only by protecting them from write, program and erase operations. when write protect (w ) is connected to v cc , the first 256 pages of memory behave like the other pages of memory.
m45pe80 signal description 9/47 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
spi modes m45pe80 10/47 3 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 4 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, hi gh or low as appropriate. figure 3 shows an example of three devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. resistors r (represented in figure 3 ) ensure that the m45pe80 is not selected if the bus master leaves the s line in the high impedance state. as the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (c) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the s line is pulled high while the c line is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). the typical value of r is 100 k , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the spi bus in high impedance. ai12836b spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r
m45pe80 spi modes 11/47 example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5s. figure 4. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
operating features m45pe80 12/47 4 operating features 4.1 sharing the overhead of modifying data to write or program one (or more) data bytes, two instructions are required: write enable (wren), which is one byte, and a page write (pw) or page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal cycle (of duration t pw or t pp ). to share this overhead, the page write (pw) or page program (pp) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory. 4.2 an easy way to modify data the page write (pw) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. the page write (pw) instruction is entered by driving chip select (s ) low, and then transmitting the instruction byte, three address bytes (a23-a0) and at least one data byte, and then driving chip select (s ) high. while chip select (s ) is being held low, the data bytes are written to the data buffer, starting at the address given in the third address byte (a7-a0). when chip select (s ) is driven high, the write cycle starts. the remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. the addressed memory page then automatically put into an erase cycle. finally, the addressed memory page is programmed with the contents of the data buffer. all of this buffer management is handled internally, and is transparent to the user. the user is given the facility of being able to alter th e contents of the memory on a byte-by-byte basis. for optimized timings, it is recommended to use the page write (pw) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (pw) sequences with each containing only a few bytes (see page write (pw) and ta bl e 1 4 : ac characteristics (50 mhz operation) ).
m45pe80 operating features 13/47 4.3 a fast way to modify data the page program (pp) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. this might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (pe) or sector erase (se) instruction. this is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. when this method is possible, it ha s the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see page program (pp) and table 14: ac characteristics (50 mhz operation) ). 4.4 polling during a write, program or erase cycle a further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (t pw , t pp , t pe , or t se ). the write in progress (wip) bit is provided in the status register so that the ap plication program can monitor its value, polling it to establish when the previous cycle is complete. 4.5 reset an internal power-on reset circuit helps protect against inadvertent data writes. addition protection is provided by driving reset (reset ) low during the power-on process, and only driving it high when v cc has reached the correct voltage level, v cc (min). 4.6 active power, stand-by powe r and deep power-down modes when chip select (s ) is low, the device is enabled, and in the active power mode. when chip select (s ) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specific instruction (the release from deep power-down mode) is executed. while in the deep power-down mode, the device ignores all write, program and erase instructions (see deep power-down (dp) ). this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.
operating features m45pe80 14/47 4.7 status register the status register contains two status bits that can be read by the read status register (rdsr) instruction. see section 6.4: read stat us register (rdsr) for a detailed description of the status register bits. 4.8 protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m45pe80 boasts the following data protection mechanisms: power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. program, erase and write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? reset (reset ) driven low ? write disable (wrdi) instruction completion ? page write (pw) instruction completion ? page program (pp) instruction completion ? page erase (pe) instruction completion ? sector erase (se) instruction completion the hardware protected mode is entered when write protect (w ) is driven low, causing the first 256 pages of memory to become read-only. when write protect (w ) is driven high, the first 256 pages of memory behave like the other pages of memory the reset (reset ) signal can be driven low to protect the contents of the memory during any critical time, not just during power-up and power-down. in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions while the device is not in active use.
m45pe80 memory organization 15/47 5 memory organization the memory is organized as: 4096 pages (256 bytes each). 1 048 576 bytes (8 bits each) 16 sectors (512 kbits, 65536 bytes each) each page can be individually: programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1) the device is page or sector erasable (bits are erased from 0 to 1). table 2. memory organization sector address range 15 f0000h fffffh 14 e0000h effffh 13 d0000h dffffh 12 c0000h cffffh 11 b0000h bffffh 10 a0000h affffh 9 90000h 9ffffh 8 80000h 8ffffh 7 70000h 7ffffh 6 60000h 6ffffh 5 50000h 5ffffh 4 40000h 4ffffh 3 30000h 3ffffh 2 20000h 2ffffh 1 10000h 1ffffh 0 00000h 0ffffh
memory organization m45pe80 16/47 figure 5. block diagram ai06812 s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c d q status register 00000h fffffh 000ffh reset 10000h first 256 pages can be made read-only
m45pe80 instructions 17/47 6 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in ta bl e 3 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read) or read status register (rdsr) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page write (pw), page program (pp), page erase (pe), sector erase (se), write enable (wren), write disable (wrdi), deep power-down (dp) or release from deep power-down (rdp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array duri ng a write cycle, program cycle or erase cycle are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected. table 3. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pw page write 0000 1010 0ah 3 0 1 to 256 pp page program 0000 0010 02h 3 0 1 to 256 pe page erase 1101 1011 dbh 3 0 0 se sector erase 1101 1000 d8h 3 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdp release from deep power-down 1010 1011 abh 0 0 0
instructions m45pe80 18/47 6.1 write enable (wren) the write enable (wren) instruction ( figure 6 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page write (pw), page program (pp), page erase (pe), and sector erase (se) instruction. the write enable (wren) instruction is entered by drivin g chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 6. write enable (wren) instruction sequence 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 7 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion page write (pw) instruction completion page program (pp) instruction completion page erase (pe) instruction completion sector erase (se) instruction completion figure 7. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m45pe80 instructions 19/47 6.3 read identification (rdid) the read identification (rdid) in struction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for numonyx. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (14h). any read identification (rdid) instruction while an erase or pr ogram cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) instruction should not be issued while the device is in deep power-down mode. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the instruction is shifted in. this is follow ed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 8 . the read identification (rdid) instruction is terminated by dr iving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 8. read identification (rdid) instruction sequence and data-out sequence table 4. read identification (rdid) data-out sequence manufacturer identification device identification memory type memory capacity 20h 40h 14h c d s 2 1 3456789101112131415 instruction 0 ai06809 q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 16 18 28 29 30 31
instructions m45pe80 20/47 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write cycle is in progress. when one of these cycles is in progre ss, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 9 . the status bits of the status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write, program or erase instruction is accepted. figure 9. read status register (rdsr) instruction sequence and data-out sequence table 5. status register format b7 b0 0 0 0 0 0 0 wel (1) 1. wel and wip are volatile read-only bits (wel is set and reset by specific instructions; wip is automatically set and reset by t he internal logic of the device). wip (1) c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m45pe80 instructions 21/47 6.5 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 10 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycl e is in progress, is rejected without having any effects on the cycle that is in progress. figure 10. read data bytes (read) instruction sequence and data-out sequence 1. address bits a23 to a20 are don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
instructions m45pe80 22/47 6.6 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (f ast_read) instruction is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 11 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_rea d) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 11. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence 1. address bits a23 to a20 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
m45pe80 instructions 23/47 6.7 page write (pw) the page write (pw) instruction allows bytes to be written in the memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page write (pw) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). the rest of the page remains unchanged if no power failure occurs and the device is not reset during the write cycle. the page write (pw) instruction performs a page erase cycle even if only one byte is updated. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 12 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. if less than 256 data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page write (pw) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (pw) sequences with each containing only a few bytes (see table 14: ac characteristics (50 mhz operation) ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page write (pw) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page write cycle (whose duration is t pw ) is initiated. while the page write cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page write cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page write (pw) instruction applied to a page that is hardware protected is not executed. any page write (pw) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
instructions m45pe80 24/47 figure 12. page write (pw) instruction sequence 1. address bits a23 to a20 are don?t care 2. 1 n 256 c d ai04045 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
m45pe80 instructions 25/47 6.8 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 13 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see table 14: ac characteristics (50 mhz operation) ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cy cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page progra m cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is hardware protected is not executed. any page program (pp) instruction, while an eras e, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
instructions m45pe80 26/47 figure 13. page program (pp) instruction sequence 1. address bits a23 to a20 are don?t care 2. 1 n 256 c d ai04044 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
m45pe80 instructions 27/47 6.9 page erase (pe) the page erase (pe) instruction sets to 1 (ffh) all bits inside the chosen page. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page erase (pe) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the page is a valid address for the page er ase (pe) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the page erase (pe) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page erase cycle (whose duration is t pe ) is initiated. while the page erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page erase cycle, and is 0 when it is co mpleted. at some uns pecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page erase (pe) instruction applied to a page that is hardware protected is not executed. any page erase (pe) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 14. page erase (pe) instruction sequence 1. address bits a23 to a20 are don?t care. 24 bit address c d ai04046 s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
instructions m45pe80 28/47 6.10 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (d). any address inside the sector (see ta b l e 2 ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in pr ogress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector that contains a page that is hardware protected is not executed. any sector erase (se) instructio n, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 15. sector erase (se) instruction sequence 1. address bits a23 to a20 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m45pe80 instructions 29/47 6.11 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in prog ress). but this mode is not the deep power- down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in ta b l e 1 1 ). to exit from deep power-down mode, the release from deep power-down (rdp) instruction must be issued. no othe r instruction must be issued while the device is in this mode. the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 16. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
instructions m45pe80 30/47 6.12 release from deep power-down (rdp) to exit from deep power-down mode, the release from deep power-down (rdp) instruction must be issued. no other instruction must be issued while the device is in this mode. the release from deep power-down (rdp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17 . the release from deep power-do wn (rdp) instruction is termin ated by driving chip select (s ) high. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the instruction to be rejected, and not executed. after chip select (s ) has been driven high, followed by a delay, t rdp , the device is put in the standby mode. chip select (s ) must remain high at least until this period is over. the device waits to be selected, so that it can receive, decode and execute instructions. any release from deep power-down (rdp) instru ction, while an erase, program or write cycle is in progress, is reject ed without having any effects on the cycle that is in progress. figure 17. release from deep power-down (rdp) instruction sequence c d ai06807 s 2 1 34567 0 t rdp stand-by mode deep power-down mode q high impedance instruction
m45pe80 power-up and power-down 31/47 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: v cc (min) at power-up, and then for a further delay of t vsl v ss at power-down a safe configuration is provided in section 3: spi modes . to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold value, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), page write (pw), page program (pp), page erase (pe) and sector erase (se) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write, program or erase instructions should be sent until the later of: t puw after v cc passed the v wi threshold t vsl after v cc passed the v cc (min) level these values are specified in ta bl e 6 . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. as an extra protection, the reset (reset ) signal could be driven low for the whole duration of the power-up and power-down phases. at power-up, the device is in the following state: the device is in the standby mode (not the deep power-down mode). the write enable latch (wel) bit is reset. the write in progress (wip) bit is reset. normal precautions must be taken for s upply rail decoupling, to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 100 nf). at power-down, when v cc drops from the operating voltage, to below the por threshold value, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.)
power-up and power-down m45pe80 32/47 figure 18. power-up timing table 6. power-up timing and v wi threshold symbol parameter min. max. unit t vsl (1) 1. these parameters are char acterized only, over the te mperature range ?40c to +85c. v cc (min) to s low 30 s t puw (1) time delay before the first write, program or erase instruction 1 10 ms v wi (1) write inhibit voltage 1.5 2.5 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
m45pe80 initial delivery state 33/47 8 initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). all usable status register bits are 0. 9 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see (1) 1. compliant with jedec std j-std-020c (for sm all body, sn-pb or pb assembly), the numonyx ecopack? 7191395 specification, and the european di rective on restrictions on hazardous substances (rohs) 2002/95/eu. c v io input and output voltage ( with respect to ground) ?0.6 v cc + 0.6 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) ?2000 2000 v
dc and ac parameters m45pe80 34/47 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. 1. output hi-z is defined as the point where data out is no longer driven. figure 19. ac measurement i/o waveform table 8. operating conditions symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c table 9. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v table 10. capacitance (1) 1. sampled only, not 100% tested, at t a =25c and a frequency of 20mhz. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0 v 8 pf c in input capacitance (other pins) v in = 0 v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m45pe80 dc and ac parameters 35/47 table 11. dc characteristics symbol parameter test condition (in addition to those in table 8 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current (standby and reset modes) s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (fast_read) c = 0.1v cc / 0.9.v cc at 25 mhz, q = open 6 ma c = 0.1v cc / 0.9.v cc at 50 mhz, q = open 8 i cc4 operating current (pw) s = v cc 15 ma i cc5 operating current (se) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 a v cc ?0.2 v
dc and ac parameters m45pe80 36/47 table 12. ac characteristics (25 mhz operation) test conditions specified in table 8 and table 9 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pw, pp, pe, se, dp, rdp, wren, wrdi, rdsr d.c. 25 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) 1. t ch + t cl must be greater than or equal to 1/ f c t clh clock high time 18 ns t cl (1) t cll clock low time 18 ns clock slew rate (2) (peak to peak) 0.03 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 10 ns t shch s not active setup time (relative to c) 10 ns t shsl t csh s deselect time 200 ns t shqz (2) 2. value guaranteed by characterizati on, not 100% tested in production. t dis output disable time 15 ns t clqv t v clock low to output valid 15 ns t clqx t ho output hold time 0 ns t shrh chip should have been deselected before reset is de-asserted 10 ns t whsl write protect setup time 50 ns t shwl write protect hold time 100 ns t dp (2) s to deep power-down 3 s t rdp (2) s high to standby mode 30 s t pw (3) 3. when using pp and pw instructions to update consec utive bytes, optimized ti mings are obtained with one sequence including all the bytes versus seve ral sequences of only a few bytes. (1 n 256) page write cycle time (256 bytes) 11 25 ms page write cycle time (n bytes) 10.2+ n*0.8/256 t pp (3) page program cycle time (256 bytes) 1.2 5ms page program cycle time (n bytes) 0.4+ n*0.8/256 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s
m45pe80 dc and ac parameters 37/47 table 13. ac characteristics (33 mhz operation) 33 mhz only available for products marked since week 40 of 2005 (1) test conditions specified in table 8 and table 9 1. details of how to find the date of marking are given in application note, an1995. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pw, pp, pe, se, dp, rdid, rdp, wren, wrdi, rdsr d.c. 33 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (2) 2. t ch + t cl must be greater than or equal to 1/ f c t clh clock high time 13 ns t cl (2) t cll clock low time 13 ns clock slew rate (3) (peak to peak) 3. value guaranteed by characterizati on, not 100% tested in production. 0.03 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 3 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 200 ns t shqz (3) t dis output disable time 12 ns t clqv t v clock low to output valid 12 ns t clqx t ho output hold time 0 ns t thsl top sector lock setup time 50 ns t shtl top sector lock hold time 100 ns t dp (3) s to deep power-down 3 s t rdp (3) s high to standby power mode 30 s t pw (4) 4. when using pp and pw instructions to update consec utive bytes, optimized ti mings are obtained with one sequence including all the bytes versus seve ral sequences of only a few bytes. (1 n 256) page write cycle time (256 bytes) 11 25 ms page write cycle time (n bytes) 10.2+ n*0.8/256 t pp (4) page program cycle time (256 bytes) 1.2 5ms page program cycle time (n bytes) 0.4+ n*0.8/256 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s
dc and ac parameters m45pe80 38/47 table 14. ac characteristics (50 mhz operation) (1) 50 mhz preliminary data for t9hx technology (2) test conditions specified in table 8 and table 9 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pw, pp, pe, se, dp, rdp, wren, wrdi, rdsr, rdid d.c. 50 mhz f r clock frequency for read instructions d.c. 33 mhz t ch (3) t clh clock high time 9 ns t cl (3) t cll clock low time 9 ns clock slew rate (4) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (4) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t whsl write protect setup time 50 ns t shwl write protect hold time 100 ns t dp (4) s to deep power-down 3 s t rdp (4) s high to standby mode 30 s t rlrh (4) t rst reset pulse width 10 s t rhsl t rec reset recovery time 3 s t shrh chip should have been deselected before reset is de-asserted 10 ns t pw (5) page write cycle time (256 bytes) 11 23 ms t pp (5) page program cycle time (256 bytes) 0.8 3ms page program cycle time (n bytes) int(n/8) 0.025 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s 1. preliminary data. 2. delivery of parts in t9hx process to start from june 2007. 3. t ch + t cl must be greater than or equal to 1/ f c 4. value guaranteed by characterization, not 100% tested in production. 5. n = number of bytes to program. int(a) corresponds to the upper integer part of a. examples: int(1/8) = 1, int(16/8) = 2, int(17/8) = 3.
m45pe80 dc and ac parameters 39/47 figure 20. serial input timing figure 21. write protect setup and hold timing figure 22. output timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai07439 c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
dc and ac parameters m45pe80 40/47 figure 23. reset ac waveforms table 15. reset conditions test conditions specified in table 8 and table 9 symbol alt. parameter conditions min. typ. max. unit t rlrh (1) 1. value guaranteed by characterizati on, not 100% tested in production. t rst reset pulse width 10 s t shrh chip select high to reset high chip should have been deselected before reset is de-asserted 10 ns table 16. timings after a reset low pulse (1) 1. all the values are guaranteed by characte rization, and not 100% tested in production. test conditions specified in table 8 and table 9 symbol alt. parameter conditions: reset pulse occurred min. typ. max. unit t rhsl t rec reset recovery time while decoding an instruction (2) : wren, wrdi, rdid, rdsr, read, fast_read, pw, pp, pe, se, dp, rdp 2. s remains low while reset is low. 30 s under completion of an erase or program cycle of a pw, pp, pe, se operation 300 s device deselected (s high) and in standby mode 0s ai06808 reset trlrh s trhsl tshrh
m45pe80 package mechanical 41/47 11 package mechanical figure 24. vfqfpn8 (mlp8) 8-lead very thin fine pitch quad flat package no lead, 6 5 mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 17. vfqfpn8 (mlp8)8-lead very thin fine pitch quad flat package no lead, 6 5 mm , package mechanical data symbol millimeters inches typ min max typ min max a 0.85 0.80 1.00 0.0335 0.0315 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e1.27? ?0.0500? ? r1 0.10 0.00 0.0039 0.0000 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 12 12 aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 d e 70-me a2 a a3 a1 e1 d1 e e2 d2 l b r1 ddd bbb c cab aaa ca a b aaa cb m 0.10 ca 0.10 cb 2x
package mechanical m45pe80 42/47 figure 25. so8 wide ? 8 lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 18. so8 wide ? 8 lead plastic small outline, 208 mils body width, mechanical data symbol millimeters inches typ min max typ min max a 2.50 0.098 a1 0.00 0.25 0.000 0.010 a2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 cp 0.10 0.004 d 6.05 0.238 e 5.02 6.22 0.198 0.245 e1 7.62 8.89 0.300 0.350 e1.27? ?0.050?? k 0 10 0 10 l 0.50 0.80 0.020 0.031 n8 8 6l_me e n cp b e a2 d c l a1 k e1 a 1
m45pe80 package mechanical 43/47 figure 26. so8n - 8 lead plastic small outl ine, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8n - 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
part numbering m45pe80 44/47 12 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device or when ordering parts operating at 50 mhz (0.11m technology, process digit ?4?), please contact your nearest numonyx sales office. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 20. ordering information scheme example: m45pe80 ? v mp 6 t g device type m45pe = page-erasable serial flash memory device function 80 = 8 mbit (1 mbit x 8) operating voltage v = v cc = 2.7 to 3.6v package mw = so8w (208 mils width) mp = vfqfpn8 6 5 mm (mlp8) mn = so8n (150 mils width) (1) 1. package available only in t9hx technology. device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape & reel packing plating technology p or g = ecopack? (rohs compliant)
m45pe80 reference 45/47 13 reference an1995: serial flash memory device marking. 14 revision history table 21. document revision history date version changes 10-feb-2003 1.0 document written 02-apr-2003 1.1 vfqfpn8 (mlp) package added 08-apr-2003 1.2 document promoted to product preview 05-may-2003 1.3 document promoted to preliminary data 04-jun-2003 1.4 description corrected of entering hardware protected mode (w must be driven, and cannot be left unconnected). document revision history for 05-may-2003 corrected. 26-nov-2003 2.0 v io (min) extended to ?0.6v, and t pp (typ) improved to 1.2ms. table of contents, so16 package, warning about exposed paddle on mlp8, and pb-free options added. change of naming for vdfpn8 package. document promoted to full datasheet 23-jan-2004 3.0 so16 pin-out corrected 28-may-2004 4.0 soldering temperature information clarified for rohs compliant devices. device grade clarified 10-may-2005 5.0 so16 wide package replaced by so8 wide package. active power, stand-by power and deep power-down modes , read identification (rdid) , deep power-down (dp) , and release from deep power-down (rdp) descriptions updated. table 20: ordering information scheme updated. figure 22: output timing updated. 4-oct-2005 6.0 added table 13: ac characteristics (33 mhz operation) . an easy way to modify data , a fast way to modify data , page write (pw) and page program (pp) sections updated to explain optimal use of page write and page program instructions. updated i cc3 values in ta bl e 1 1 : d c characteristics . updated table 20: ordering information scheme ecopack? information added. 14-feb-2006 7 x process technology added (see section 2.5: reset (reset) , table 14: reset timings for u process technology devices and ta bl e 1 5 : r e s e t timings for x process technology devices ). mlp package renamed as vfqfpn8, mlp silhouette modified on page 1 . t lead removed from table 7: absolute maximum ratings . table 5: status register format moved from section 4.7: status register to section 6.4: read status register (rdsr) . blank option removed under plating technology in table 20: ordering information scheme .
revision history m45pe80 46/47 15-dec-2006 8 50 mhz frequency added, table 14: ac characteristics (50 mhz operation) added. small text changes. section 2.5: reset (reset) updated. v cc supply voltage and v ss ground descriptions added. figure 3: bus master and memory devices on the spi bus modified and explanatory text added. behavior of wip bit specified at power-up in section 7: power-up and power-down . v io max modified and t lead added in table 7: absolute maximum ratings . table 15: reset conditions and table 16: timings after a reset low pulse updated. so8n package added (t9hx technology only), so8w and vfqfpn8 package specifications updated (see section 11: package mechanical ). 10-dec-2007 9 applied numonyx branding. table 21. document revision history date version changes
m45pe80 47/47 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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